Charge-based MOS correlated double sampling comparator and folding circuit
نویسندگان
چکیده
A novel charge-based comparator and folding circuit are presented. Correlated double sampling comparison is performed using a log-domain integrator, implemented by a subthreshold MOS transistor with the source coupled to a capacitor. The circuit produces a current that is a logistic function of the change in voltage on the gate, with an input-referred offset voltage that is a logarithmic function of time. Folding operation for analogto-digital conversion is obtained by differentially combining currents from a bank of these comparators. A prototype 128-channel parallel 4-bit gray-code analog-to-digital converter has been implemented in a 0.5 m CMOS process, delivering 128 MS/sec at 76 mW power dissipation.
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